What surprised me was that this entire walk is fully hardware-driven -- no microcode involvement at all. The state machine reads the page directory entry, reads the page table entry, checks permissions, and writes back the Accessed and Dirty bits, all autonomously. Since it's hardware-driven, it runs in parallel with the microcode and needs its own memory bus arbitration -- the paging unit must share the bus with both data accesses from the microcode and prefetch requests from the instruction queue.
5CB -4 DLY IN+= ; delay slot 3: IND points to low DWORD
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* @param arr 待排序数组